Phase locked loops (PLLs) have important uses in communications applications. One such use, a PLL frequency synthesizer, generates an output signal having a programmable frequency to be used in tuning two or more communication channels. A reference oscillator generates a reference signal which is counted in a reference counter to provide a first input of a phase detector. An output of a loop counter provides a second input of the phase detector. The phase detector provides a voltage indicative of whether the inputs thereof are in lock, i.e. have the same phase and frequency. The phase detector output is filtered in a loop filter such as an integrator, the output of which provides an input to a voltage controller oscillator (VCO). The output of the VCO, which is the output of the PLL frequency synthesizer, is then divided in the loop counter. If a different output frequency is desired, the user need only change the starting counter value of the reference counter or the loop counter, and the feedback loop of the PLL frequency synthesizer causes the output frequency to quickly lock.
In many applications, the output of the VCO has a relatively large frequency in relation to the reference frequency. For example, the VCO may be programmed to output a signal having a frequency of 1.2 gigahertz (GHz). Because this frequency is too high for division in complementary metal-oxide-semiconductor (CMOS) circuitry, the loop counter is usually broken down into two components: a prescaler, and a subsequent counter also referred to as the loop counter. The prescaler can then be made with higher-speed bipolar circuitry, while the loop counter is implemented in CMOS circuitry.
Low power consumption is a key consideration in many products using PLL frequency synthesizers. Thus, these products often place the PLL frequency synthesizer in a standby mode to save power. While in standby mode, the prescaler, counters, and phase detector are disabled to save power. The input to the VCO remains substantially constant, causing the VCO output to maintain approximately the same frequency as before the PLL frequency synthesizer entered standby. This creates a problem on exiting standby, however. During standby, the output of the VCO may have drifted in phase, but not in frequency. Additionally, when the counters are re-enabled, they are not synchronized and the phase detector will detect a large error, even though this error reflects a change in phase rather than in frequency. Because of the spurious detection of this large error, the VCO changes its output frequency even though the desired frequency may be correct. Thus, the PLL takes an undesirably long time to lock.
In addition, integrated circuit prescalers commonly do not have reset inputs. These integrated circuits need low pin counts to minimize cost. In addition, they would require an extra switching transistor stacked in each stage to incorporate a reset function, increasing voltage requirements and power consumption and size. Thus, what is needed is a PLL frequency synthesizer which locks quickly after standby and which interfaces easily to available prescaler circuits.